1. Field of the Invention
The present invention relates generally to a high-speed sense amplifier for use in programmable logic devices (PLD), and more particularly, to such a sense amplifier having a variable current level trip point.
2. Description of the Related Art
Dynamic random access memory (DRAM) and static random access memory (SRAM), directly store different voltage levels (e.g., via a storage capacitor in a DRAM) corresponding to the stored logic states. Non-volatile semiconductor memory cells, however, store data by having two different current levels through the cell, and "ON" cell current level, and an "OFF" cell current level. When such non-volatile memory cells are used in a logic device, the different cell currents must be translated or converted by a sense amplifier for output of a signal indicative of the state of the stored data.
As further background, and referring now to FIG. 1, a programmable logic device (PLD) 10 is shown and which includes a memory array 12, and a sense amplifier 14. Those skilled in the art will recognize the well-known purpose and function of the input terms IT1, . . . , ITN and the read product term, particularly as used in a PLD or complex PLD. Memory 12 and sense amplifier 14 are coupled together by a read product term (RPT) line 16, and a verify (VRFY) line 18, which also serves as a virtual ground line 18. The memory array 12 is of the type having non-volatile memory cells M.sub.1, . . . , M.sub.n, and select gates N.sub.1, . . . , N.sub.n connected in series. In particular, the memory cells M.sub.i include a respective floating gate 20.sub.1, . . . , 20.sub.n. As is well-known in the art, when the floating gate has been programmed, the particular memory cell so programmed will not conduct upon application of a gate voltage VREF1. However, when the floating gate is not programmed, the memory cell will conduct, and will carry current. Moreover, each one of the plurality of select gates has an input term IT1, . . . , ITN applied to a respective gate terminal. Thus, when a memory element M.sub.i is programmed to be conductive, and the series-connected select gate is turned-on by application of an appropriate input term, the "branch" or "leg" so formed may carry current between the RPT line, and the virtual ground. Many branches are disposed in parallel between the RPT line and the virtual ground line to generate a product term.
Sense amplifier 14 includes a first stage 22, and second stage 24. The first stage 22 is included for providing a substantially constant voltage potential on the RPT line, and for sensing whether current is being drawn through any one of the plurality of branches formed in memory array 12. The sensing is accomplished by way of feedback circuits. In one embodiment of sense amplifier 14, the amplified signal at the output of first stage 22 has a swing of approximately 1 volt. Second stage 24 then further converts this signal to full CMOS levels.
In operation, the sense amplifier output (SAOUT) is normally high when none of the plurality of branches in memory array 12 are conductive. When one or more of the branches of memory array 12 become conductive, the current drawn through memory 12 via the RPT line, causes the sense amplifier 14 to "trip," thus causing the sense amplifier output to assume a low state. Current limiting transistor 26 is provided to limit the total current through memory array 12 by elevating the voltage potential of virtual ground line 18 according to the amount of current being carried through the plurality of branches. Specifically, as more branches in memory array 12 become conductive, the current flowing through the channel of current limiting transistor 26 causes the drain terminal of the transistor (which is connected to virtual ground line 18) to rise. The rise in the voltage potential of virtual ground line 18, relative to the voltage on RPT line 16, causes the voltage drop across the memory array to be reduced. This reduction in voltage differential reduces the aggregate current flow through the conductive branches.
The circuit shown in FIG. 1, however, can produce incorrect and inconsistent results (i.e., a "glitch") under certain, transient switching conditions. One example of a such a condition is a so-called "strong zero" to "weak zero" glitch. A "strong zero" is when many branches are conductive, which causes SAOUT to go low or be a zero. A "weak zero" is when only one branch is conductive, which is nonetheless still sufficient, during steady state, to make SAOUT go low. This glitch occurs as follows: Assume all of the memory elements M.sub.1, . . . , M.sub.n, are programmed to a conductive state. When, initially, a large number or all of the select gates N.sub.1, . . . , N.sub.n are on (i.e., a "strong zero" condition), SAOUT will be low, and the voltage level on line 18 will be very close to that on line 16. However, when the input terms IT1, . . . , ITN change state such that all but one of the select gates are turned-off simultaneously, the current flow through the remaining one conductive memory element at this transition time is below the trip point of sense amplifier 14. This is due to the fact that the voltage difference between lines 16 (RPT) and 18 (VRFY) is very small, and accordingly, a very small current flows. The sense amplifier output SAOUT will switch high momentarily, until current limiting transistor 26, such as device N4, pulls down line 18 to a relatively lower potential (i.e., closer to hard ground), so that enough of a voltage drop is developed across the lone conductive memory element/select gate to support a current flow higher than the trip point of sense amplifier 14. Such a condition is undesirable, and may be unacceptable in certain situations.
Accordingly, there is a need to provide an improved high-speed sense amplifier that eliminates or minimizes one or more of the problems as set forth above.